On the Stability and Robustness of Non-Synchronous Circuits with Timing Loops

Among the most pressing issues in current deep submicron VLSI circuits are large parameter variations, primarily caused by process technology imperfections, that result in excessive delay variations, and continuously increasing soft error rates. The former seriously challenges the classic synchronous design paradigm, and coping with the latter requires suitable fault-tolerant architectures. In this paper, we present first results of the parameter sensitivity analysis of our DARTS fault-tolerant clock generation scheme. Unlike conventional clocking techniques for GALS systems, DARTS does not use quartz oscillators, but generates approximately synchronized clocks by means of an asynchronous distributed algorithm. Initially, both measurement and simulation results indicated deterministic fluctuations of the DARTS clock frequency, which depend strongly on the delay parameters, but could not be explained by noise or dynamic parameter variations. By means of non-linear control theory we develop an explanation of these effects, and establish that any non-trivial closed-loop asynchronous circuit exhibits such deterministic timing variations. Our simulation results confirm that majority voting, as employed to attain fault-tolerance in DARTS, improves the robustness against parameter variations, but also considerably increases the complexity of the underlying control theory problem.